Target devices such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and structured ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices.
Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are high-level compilation and hardware description language (HDL) compilation. EDA tools that perform high-level compilation allow designers to more quickly realize designs for systems by raising the abstraction level from traditional register transfer level (RTL) based design. However, certain aspects of system design are inescapable and continue to provide challenges for designers. On such aspect is timing closure where all clocks must meet their respective fixed timing constraints.
Traditionally, when timing closure is not met after an initial high-level compilation and HDL compilation run, additional iterations of the design process are needed to modify the hardware design and further analyze the timing of the design. This may require a significant amount of time which can be undesirable.